The present invention relates to a frequency doubling circuit having an integrator to which an input signal having a given frequency can be supplied, and at whose output an integrated signal is provided. The frequency doubling circuit also has a quantizer at whose output a quantized signal derived from the integrated signal is provided, and has an exclusive OR gate to which the input signal can be supplied at a first input thereof and to which the quantized signal can be supplied at a second input thereof, and at whose output an output signal having twice the frequency of the input signal is provided.
Circuits that generate a signal having twice the frequency of a provided signal are for example required for a data transmission on a data bus in which a clock signal having half the data rate is provided. In this context, receiver circuits can be provided that, for further processing, derive from the received clock signal having half of the data rate a clock signal having the frequency of the full data rate.
A known frequency doubling circuit of this type is shown in FIG. 3. Here, an input signal U1 having a frequency that is to be doubled is supplied to an exclusive OR gate directly in an unmodified form on the one hand, and in integrated, quantized form on the other hand. An integration and a subsequent quantization generate, at the output of the quantizer Q, a signal U4* that is phase-shifted by 90xc2x0 in relation to the input signal U1. At the output of exclusive OR gate EXOR, an output signal U5* having twice the frequency of the input signal can be derived.
A frequency doubling circuit of this type is described for example in published, Non-Prosecuted German Patent Application No. DE 22 129 11 A.
However, in real frequency doubling circuits according to FIG. 3, there is the problem that in particular the quantizer Q has a signal runtime or delay that has the effect that the signal that is to be phase-shifted by 90xc2x0 is in fact shifted by a larger phase angle. The additional, undesired phase shift is disturbing particularly at high operating frequencies, because here even small delays correspond to large phase angles. The consequence of the additional phase shift is that the frequency-doubled output signal has a distorted impulse-pause ratio, as is shown in FIG. 4 for output signal U5*.
The described problem can be solved by emulating the signal runtime or signal delay of the quantizer with an equally large additional runtime in the path of the input signal at the input side at the exclusive OR gate. However, this has the disadvantage that a clock signal generated in this way no longer has the correct phase with respect to the data signals coming into a receiver. Here, all incoming data signals would have to be delayed by the same phase angle, which, in particular given broad data buses of for example 64 bits, and high data rates such as for example 1 gigabit/second, results in an increased outlay, requires a large chip surface, and increases power loss.
It is accordingly an object of the invention to provide a frequency doubling circuit which overcomes the above-mentioned disadvantages of the heretofore-known frequency doubling circuits of this general type and which avoids a distortion of the impulse-pause ratio while maintaining the phase position of the clock signal.
With the foregoing and other objects in view there is provided, in accordance with the invention, a frequency doubling circuit, including:
an integrator configured to receive an input signal having a first frequency, the integrator having an integrator output and providing an integrated signal at the integrator output;
an adder connected to the integrator and configured to receive the input signal and the integrated signal, the adder having an adder output and providing a summed signal at the adder output;
a quantizer connected to the adder and having a quantizer output, the quantizer receiving the summed signal, deriving a quantized signal from the summed signal and providing the quantized signal at the quantizer output; and
an exclusive OR gate having a first input, a second input and an output, the exclusive OR gate receiving the input signal at the first input and receiving the quantized signal at the second input, and providing an output signal having a second frequency, the second frequency being double the first frequency.
In other words, the frequency doubling circuit according to the invention includes:
an integrator to which an input signal having a first frequency can be supplied and at whose output an integrated signal is provided;
a quantizer at whose output a quantized signal derived from the integrated signal is provided;
an exclusive OR gate to which the input signal can be supplied at a first input, and to which the quantized signal can be supplied at a second input, and at whose output an output signal having twice the frequency of the input signal is provided; and
an adder to which the input signal and the integrated signal can be supplied at the input side, and at whose output the quantizer is connected for supplying a summed signal to the quantizer.
The introduction of an additional adder between the integrator and the quantizer has the advantage that the phase position of the input signal is not influenced by additional runtime effects. In addition, through suitable addition of the input signal to the integrated input signal, the signal delay is compensated by runtime effects in the quantizer. At the output of the exclusive OR gate, an output signal is provided that has twice the input signal frequency and that has a symmetrical impulse-pause ratio. Advantageously, no additional runtime delays or phase shifts occur in the input signal path. The described frequency doubling circuit can be realized with a low chip surface requirement and can be operated with a low power loss. Moreover, the described frequency doubling circuit is suitable for high data rates.
In an advantageous embodiment of the present invention, the adder has a weighting unit for weighting the input signal. The summed signal is thereby formed from the weighted input signal and the integrated signal. Using a weighted adder, a compensation of these runtime effects that is adapted precisely to the runtime delay of the quantizer is possible through weighted addition. The weighting factor is thereby dependent on the one hand on the runtime delay in the quantizer and on the other hand on the integration time constant of the integrator. Through the weighted addition of the input signal to the integrated signal, in the output signal of the adder, the summed (added) signal is shifted both in its rising and also in its falling edge in such a way that the runtime caused by the quantizer is compensated, and the output signal has an undistorted and symmetrical impulse-pause ratio of 1 to 1. In addition to the runtime of the quantizer, other runtime effects, for example in the integrator, in logical gates or on lines can of course also be taken into account and correspondingly compensated.
In a further advantageous embodiment of the present invention, the integrator is an RC low-pass filter. Because in the specified circuit configuration only low demands are made on the precision of the integration in the integrator, the integrator can be realized simply as an RC low-pass filter.
In a further advantageous embodiment of the present invention, the quantizer is a limiting amplifier. A limiting amplifier, which allocates a value-discrete output signal to a value-continuous input signal, can be realized in a simple fashion. The limiting amplifier can thereby be configured such that the quantized signal can assume only two discrete states, namely a logical zero or a logical one.
In a further advantageous embodiment of the present invention, the quantizer provides a logical one at its output if the voltage of the summed signal is greater than or equal to zero, and provides a logical zero if the voltage of the summed signal is less than zero. The voltage of the summed signal is here related to the AC component of this voltage. Of course, the summed signal can also include a DC component.
According to another feature of the invention, the weighting unit weights the input signal such that zero transitions of the summed signal are shifted for compensating runtime effects in the quantizer.
According to yet another feature of the invention, the weighting unit weights the input signal such that zero transitions of the summed signal are shifted for compensating a sum of runtime effects in the integrator, in the quantizer, and in the exclusive OR gate.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a frequency doubling circuit, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.